High data reliability, high speed of memory access, lower power consumption and reduced chip size are features that are demanded from semiconductor memory. In recent years, three-dimensional (3D) memory devices, such as High Bandwidth Memory (HBM), with considerably smaller footprints have been introduced. Some 3D memory devices are formed by stacking dies vertically and interconnecting the dies using through-silicon vias (TSVs) between an interface (I/F) die and core dies as shown in FIG. 1A. The TSVs in the 3D memory devices reduce circuit delays and power consumption due to long signal lines in a non-3D memory device. A large number of TSVs in the 3D memory devices between layers allow wide bandwidth buses between functional blocks in different layers. Thus, the 3D memory devices contribute to higher memory access speed, lower power consumption and chip size reduction.
FIG. 1B is a cross-sectional view of a structure of TSVs in the HBM in FIG. 1A. As shown in FIG. 1B, a TSV 1 in an interface chip 2 is through silicon substrate layers 3 and wiring layers 7. An insulating ring 4 surrounds the TSV 1. The TSV 1 is insulated from an internal circuit 6 formed at least in part in a transistor region 5 in the silicon substrate layers 3 and wiring layers 7. Thereby, capacitance between the TSV 1 the silicon substrate layers 3 is reduced. A surface bump 9 is disposed at an end of the TSV 1 on a side of a core chip 8 of the silicon substrate layers 3. The surface bump 9 may be an electrode that contacts a surface bump 10 provided in a core chip 8. For example, the surface bump 9 is coupled to a plurality of pads 11 through the TSV 1. The plurality of pads 11 may be formed in the wiring layers 7. A through-hole electrode 12 may couple the plurality of pads 11 to each other in the wiring layers 7. Further, the plurality of pads 11 is coupled to the internal circuit 6 through internal wiring lines (not shown in the drawings).
A TSV in HBM may have a parasitic resistance and a parasitic capacitance, which may cause a delay of a signal between an I/F die and a core die transmitted through the TSV. Particularly, capacitance of the TSV may be frequency dependent and effective capacitance (Ceff) of the TSV may appear to be different, depending on a frequency of the signal. FIG. 2A is a graph showing a capacitance-voltage (CV) characteristics curve showing relationships between a voltage of the TSV (VTSV) and capacitance of the TSV (CTSV) in a p-type Si substrate. A horizontal axis represents the voltage of the TSV (VTSV) and a vertical axis represents the capacitance of the TSV (CTSV). A signal represented as the voltage of the TSV (VTSV) swings between two voltages +V and −V. When the signal level is negative, the CV characteristics curve is in an accumulation phase and the capacitance of the TSV (CTSV) is about capacitance of an oxide-semiconductor interface (Cox) per area. In a depletion phase, the capacitance of the TSV (CTSV) decreases as a more positive voltage (VTSV) is applied on the TSV. In an inversion phase, the effective capacitance (Ceff) of the TSV varies based on a frequency of the signal. For example, the capacitance of TSV (CTSV) increases to Cox if the frequency of the signal transmitted through the TSV is low due to that holes and electrons in the p-type Si substrate inverts its substrate type responsive to gate signals and electron accumulation. On the other hand, the capacitance of TSV (CTSV) may stay depleted, smaller than Cox, if the frequency of the signal transmitted through the TSV is high.
FIG. 2B is a graph showing capacitance-frequency characteristics showing relationships between a frequency of a signal transmitted by a TSV (FTSV) and effective capacitance of the TSV (Ceff) in an inversion phase. A horizontal axis represents the frequency of the signal transmitted by the TSV (FTSV) and a vertical axis represents the effective capacitance of the TSV (Ceft). As shown in FIG. 2B, the effective capacitance of the TSV (Ceft) becomes smaller as the frequency of the TSV (FTSV) becomes higher, while the frequency of the signal is between a first threshold frequency (FREQ1_INV) and a second threshold frequency (FREQ2_INV). For example, the effective capacitance of the TSV (Ceff) is stable around 1.5e-13 F when the signal has a frequency (FTSV) lower than the first threshold frequency (FREQ1_INV). The effective capacitance of the TSV (Ceff) starts dropping when the frequency FTSV becomes higher than the first threshold frequency (FREQ1_INV). If the signal has the frequency FTSV higher than the second threshold frequency (FREQ2_INV), the effective capacitance of the TSV (Ceff) becomes stable. As a result, a signal having a low frequency, particularly lower than the first threshold frequency (FREQ1_INV) may have a longer delay in transmission through a TSV due to higher effective capacitance (Ceff) than a signal having a high frequency.
FIG. 3 is a timing diagram of sets of a clock signal, a control signal (command signal) and an address/data signal through a TSV on a transmitter side and on a receiver side. The timing diagram is based on the signals transmitted from a transmitter side (e.g., the interface die) to a receiver side (e.g., the core die). A horizontal axis represents a time and a vertical axis represents a signal level (e.g., logic high, logic low). The clock signal is set to a logic high level and to a logic low level alternatively every half cycle the clock signal. The control signal and the address/data signal may be set to a logic high level or a logic low level, depending on the signal levels to be transmitted every cycle. Thus, a frequency of the clock signal is twice or more than the frequencies of the control signal and the address/data signal. A TSV transmitting the clock signal CKtx from the transmitter side to the receiver side as the clock signal CKrx may have a smaller effective capacitance (Ceff), if the frequency of the clock signal is high enough to cause small effective capacitance (Ceti) of the TSV. On the other hand, a TSV transmitting the control signal CTRLtx from the transmitter side to the receiver side as the control signal CTRLrx may have a larger effective capacitance (Ceff) because of having a frequency that is half or less than the frequency of the clock signal. Similarly, a TSV transmitting the address/data signal ADDtx/DATAtx from the transmitter side to the receiver side as the control signal ADDrx/DATArx may have a larger effective capacitance (Ceff) because of having a frequency that is half or less than the frequency of the clock signal. Due to the smaller effective capacitance (Ceff) of the TSV for the clock signal, a clock signal CKrx may have shorter delay. At the same time, the larger effective capacitance (Ceff) of the TSVs for the control signal and the address/data signal, the control signal CTRLrx and the address/data signal ADDrx/DATArx may have longer delays. The above finding is a result experimentally observed by the inventors. The inconsistent delays across signals due to different signal frequencies may cause transmission errors.